By Ib M. Skovgaard
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MemRead = 1: All instructions will work correctly. ) Solution* for Chapter B ExardsM f. MemWrite = 1: Only sw will work correctly. The rest of instructions will store their results in the data memory, while they should not. 7 No solution provided. 42. 18 on page 308 to implement the j r instruction and a new column to produce the JumpReg signal. 18 on page 308. The ALU will identify the s 11 operation by the ALUop field. 13 on page 302 should be modified to recognize the opcode of si 1; the third line should be changed to 1X1X0000 0010 (to discriminate the a d d and s s 1 functions), and a new line, inserted, for example, 1X0X0000 0011 (to define si 1 by the 0011 operation code).
40). d. This is an asynchronous exception event that can occur at any cycle. We can design this machine to test for this condition either at a specific cycle (and then the exception can take place only in a specific stage), or check in every cycle (and then this exception can occur at any processor stage). e. Check for instruction memory address can be done at the time we update the PC. This can be done in cycle 1. f. Check for data memory address can be done after address calculation at the end of cycle 3.
MemtoReg can be replaced by RegDst, ALUSrc, MemRead, or ALUOpl. Branch and ALUOpO can replace each other. 32 We use the same datapath, so the immediate field shift will be done inside theALU. 1. Instruction fetch step: This is the same (IR <= Memory[PCl; PC <= PC +• 4) 2. Instruction decode step: We don't really need to read any register in this stage if we know that the instruction in hand is a 1 u 1, but we will not know this before the end of this cycle. It is tempting to read the immediate field into the ALU to start shifting next cycle, but we don't yet know what the instruction is.
Analytic statistical models by Ib M. Skovgaard